This emulsion relates to fabrication of semiconductor devices, and more particularly to a method of reducing capacitance between interconnect lines in such circuits or devices.
An integrated circuit includes numerous conductors extending across the topography of a substrate. Components within a system are electrically connected by sets of interconnect lines or conductors. With a constant trend towards decreasing the size of integrated circuits and increasing the capacity of circuits of a specific size, the number of interconnects per integrated circuit or semiconductor device has been on the increase. This has resulted in a decrease or reduction in spacing between interconnect lines on a single device. However, as the spacing between interconnect lines is reduced, intralevel capacitance between the interconnect lines increases.
It is important, therefore, to reduce the capacitance between interconnect lines to minimize cross-talk between them and decreases in semiconductor device speed.
A number of different expedients have been proposed and/or used to reduce the intralevel capacitance between interconnect lines in a semiconductor device. One such approach in general has been to use a material having a low dielectric constant between the interconnect lines. Note, however, that air has a relative dielectric constant of 1.0, substantially lower than the dielectric constants of most other materials conventionally used. For this reason, some approaches in the prior art to the problem of reducing capacitance between interconnect lines in a single device have involved the creation of air voids between the interconnects.
One such process is described in U.S. Pat. No. 5,641,712 of Grivna et al. In this process a first conventional dielectric layer is disposed over a device comprising a number of interconnect lines disposed over a substrate. The dielectric layer, which may be a nitride or preferably an oxide formed from a silane source gas using a chemical vapor deposition (CVD) process, forms what is termed in that patent "breadloaf" shapes over the interconnect lines. The dielectric layer is then etched to remove a top portion of it and leave spacers formed by the bottom portions around the interconnect lines. Then, an additional deposition process is used to provide an electrically insulating layer or dielectric layer over the spacers, the interconnect lines and the substrate. The gaps between the interconnect lines and spacers are nearly but not completely filled in by the dielectric layer. Then, an etch, preferably a sputter etch, is used to redistribute the material in the dielectric layer, closing off the part of the gaps to produce sealed air-filled voids between the interconnect lines. One or more additional layers of material may be then deposited atop the overall device.
Another process which produces air-filled voids is described in U.S. Pat. No. 5,759,913 of Fulford et al. In this process an hygroscopic dielectric is disposed on the substrate between interconnect lines. A dielectric material is then deposited on the device, forming structures similar to the "breadloaf" structure of Grivna et al. This deposition is preferably carried out by CVD and uses typical materials such as oxide, nitride, and/or oxynitride. The deposition temperature is chosen to be one which permits outgassing or desorption of moisture from the hygroscopic dielectric during the deposition process. Such outgassing minimizes or substantially prevents deposition of the dielectric on the substrate or on the lower surfaces of the interconnects just above the substrate. Then, a fill dielectric is deposited on the previously deposited dielectric, particularly on the upper surface or sidewalls of the hygroscopic dielectric. This deposition is carried out at a lower temperature which does not trigger sufficient amounts of outgassing necessary to overcome deposition upon the material. This results in an air-filled void which is said to be completely encased between the two deposited dielectrics.
The processes described in both of these patents produce voids which extend above the upper surfaces of the adjacent interconnects (and optionally even below the lower surfaces of such interconnects). These processes are quite satisfactory for producing air voids between interconnects in which both the interconnects and the void are covered by a layer of material such as dielectric from that point forward in the process. However, in a more recently developed process, such as that described in U.S. Pat. No. 5,504,569, planarizing or polishing is carried down to the top surface of interconnects and/or below. This processing step would break through the top of any air voids formed according to the Grivna et al. or Fulford et al. processes, thus destroying their usefulness, since any subsequent treatment would simply fill the (now broken) voids with material having a higher dielectric constant than air.
This invention provides a process for producing air voids between interconnects and similar structures in semiconductor devices in which the air filled voids terminate below the uppermost surfaces of such structures which are to be exposed in subsequent planarization or similar processing.